The second slide. For anybody who just walked in, I'm Todd Fernandez. I have a handle in the program. I don't care, I just really didn't want my name associated with this on the web. So my name's Todd Fernandez. I'm here to talk about semiconductors. There's a QR code on here if you want to follow along on your iPad, Android device, or other. You can go ahead and click that, it'll take you to a dropbox, and you can follow along on the slides. So I called it inseparable from magic. I'm an engineer, I kind of find the term magic a little bit insulting when people refer to my work, or the work of other engineers, because it's not magic, it's sweat, and blood, and mental stability that goes into these things to make them work. I use the term inseparable from magic because from working in the industry, I can tell you that's a fairly standard response. What happened? We don't know. Why does it work? It's magic. And that's from the people who know. So, inseparable from magic. What you're looking at here is the first ever solid state transistor, Bell Labs 1947. If you haven't read the book, The Idea Factory, it talks about this in detail. It's incredible. So, disclaimers. Read the disclaimer, I'm going to talk about something else. I'm going to leave time at the end for questions. If you have a question, everything has a slide number in the bottom right, which we can actually see, which is fantastic. Please reference the slide number, it helps me out with answering your question in a little more detail. At the end, if you missed the download link, I have the download link. People who are listening to just audio, there's a download link at the end I will read out. I hate that this slide is necessary, but semiconductor companies kind of make the federal government look silly in terms of IP security, and like I said, I like this industry to work for. So, this is me. I have a degree in mechanical engineering, I've worked in four different fabs, I've worked in a wide range of weird things from micro lithography to micrometrology to thin films deposition to what we call yield analysis. I've worked in a range of things from academic research to development to production. That's me at work. So, I blurred out my badge. I shouldn't have that picture, that's a good story. So, what are we talking about? Let's do a little statistics first. This is a human hair, scaled up. 40 micron diameter human hair, that's a fairly average human hair. In 1971, Intel released the Intel 4004. That was a 10 micron device line size. So, that's a scaled 10 micron. That's in 1971. Here's 1990. 800 nanometers. Here's 2000. 130 nanometers. Can everybody see that dot? If you can't see that dot, raise your hand. Okay. There's a dot there. That's 2010, two years ago. 32 nanometer is in relation to a human hair. I did the math at one point, you can put something like a gigabyte of information nowadays, you could store a gigabyte in a human hair with modern transistor technology. So, this is the basis. Do we know how a transistor works? So, from a semiconductor solid state physics standpoint, there are six major parts to a transistor. You have a substrate. That is the silicon wafer, the background, kind of the bottom of it. That's what everything is built on top of. You have a source and a drain. Those are effectively think of them as the terminals. They're where you plug in the wires. One's positive, one's negative. What we do is we put impurities, dopants, things like phosphorus, arsenic, other stuff, I'm just going to say other stuff, into the surface of the wafer, changing the electrical characteristics of it, so that we can make it more or less electrically conductive, electrically resistive, things like that. On the top we have a gate insulator. That insulates the gate material, which is where we flow the current that is the on and off switch, from the body of the transistor here. The last thing on top is the gate itself. What happens in a transistor is we flow electricity through the gate. That generates a field. That enables us to turn the transistor on and off. Here's what it looks like in practice. This is a research transistor. This is not anything you will ever see in manufacturing. What you're seeing here are electrical test pads so that anyone who wants can connect to the transistor. That kicks down into contacts, which are where they actually access things, a source, a drain, and a gate. If we add power to this with an electrical bias across these two, adding power here connects these two. Here's how it looks in, I guess, Microsoft art. As we apply a positive voltage, we begin to form what's called a pinched channel. That's electricity beginning to flow across the transistor. As we continue to turn it more and more on, on and off become relative, which is fun. This is what happens. We actually begin to fully form an on transistor. The parlance that is used in the industry is electrons and holes. Electrons go this way. Electron holes, or the absence of electrons, go that way. If you think back to high school chemistry, you remember valence electrons. A lot of materials have either one or two elements in their outer valence. A lot of materials have one or two holes in their outer valence. We deal in trading electrons for holes as they move across. That's how we create flow. First thing that's going to break your mind, transistors are not digital. We make digital logic circuits out of them, but they're not digital. This is what the electronic response curve of a transistor looks like. On the top, on the y-axis here, you have effectively current that is flowing across the transistor. On the bottom, you have how much voltage we're applying to the gate. There are four things you should keep an eye on here. This is off. If you notice, we're looking at this is a log scale, so one to the negative second. One times ten to the negative second. That's not zero. On is kind of a nebulous state where it's mostly on. We start to talk about things in terms of the threshold voltage. The threshold voltage is where we get that shoulder, where things start to turn on, where things start to behave like they're on and not off. Everybody talks about power and heat in transistors and computer chip usage. This is effectively the majority of what they're talking about. They're talking about leakage. The fact that our off state is not as off as it could be, which is a term that kind of messed with me for a while when I started in this industry, being offer is very, very important. Basics of construction. We're going to talk through some of the tools, some of the technology they're using to manufacture these. Then we're going to get into what the transistors actually look like nowadays. First of all, a fab. Everybody knows at least what a fab is. You guys probably think of them. Bunny suits, Intel commercials, lots of stuff. This is what a fab actually looks like. It's about four to five levels. This is a picture of Samsung's brand new, spanking new fab in Austin, Texas. Nowadays they're using what's called 300 millimeter wafers. We'll talk about that next slide. Usually modern fabs are about 300,000 square feet of manufacturing space. That's large. Now consider what's known as a class one clean room. Class one clean room means there is one half micron particle, one, per cubic foot. I didn't mix units. You can talk to ISO about that. As a reference, everybody's familiar with operating rooms. Operating rooms are class 10,000. If you wanted to have surgery, this is probably a better place. Wafers. Wafers are cool. These are what we manufacture on. They are pulled, they are actually a single crystal. Everybody think back to crystals and science and chemistry. If I were to take, this is an ingot, they grow them like this in a furnace like this using something called the Kralski, I can't, I can never pronounce this word, process. It's on wiki, look it up. They make ingots. We make ingots that are literally a single crystal and then we slice them into individual wafers. That ingot, if I could look at it on a molecular scale from a atomic standpoint, I could take it, I could turn it on end, cut off the front, cut off the back, and look through a hole between all of the atoms from the front to the back. They all line up perfectly. That's very important because it's the only way they can make the process work. Contamination levels, about .1 parts per billion is the acceptable higher limit. 2011 earthquake in Japan cut worldwide wafer production by 25%. Scared the heck out of everyone. Reason is that's a big furnace that melts silicon. When the power goes off to it, what happens? It all crystallizes. It's now junk. It has to be replaced. Restart takes about a month. Wafer size, everybody's probably thinking, so we make these in circles? Yeah, we make them in circles. This is like 1955 one-inch wafers. Dime nickel size, right? Nowadays, everybody who's anybody uses 12-inch wafers. It's about the size of a dinner plate. We're doing 22 nanometer feature size on something the size of a dinner plate with as darn close to 100% accuracy as we could. There's an initiative called the Global 450 Initiative up in Albany. They're making 450 millimeter technology work. This is a 12-inch wafer. If anyone wants to know what a 12-inch wafer is, put your thumbs together. This is the diameter outside of your fist. This is about 6 inches. Those are 18 inches. That's very very very large. Front opening unified pods. I talked about clean rooms. Modern fabs, you don't touch wafers. You don't handle wafers. Even with two pairs of gloves on, the salt from the sweat on your skin will contaminate them. They're trashed. Like I said, front opening unified pods. That's where we put the silicon wafers when we manufacture them. They are totally handled automatically by robotics. They are held at sub-class one. Our clean room, our class one clean room, is no longer clean enough to make these things work. If you remember back to the first slide, human hair versus what the device size is, you can see why that kind of happens. It prevents contamination. They also color code them to prevent contamination, I guess, inter-contamination between wafers at different stages of manufacturing. A tool. This is lithography. Lithography is, to a large extent, the core technology of semiconductor manufacturing. I say core because for years and years and years and years and years, it's usually been the technological limiter in terms of making things smaller. I know if anybody in here knows this field, I'm probably stretching it a little bit, but lithography is important. Lithography is photography on a very weird scale. What happens is we coat the wafer in a thing called photoresist. It's a photoreactive chemical. We then have a pattern, a reticle, a mask, there's interchangeable terms for it, and shine a very, very bright light through it and print it on the wafer. There's two pieces of equipment involved in doing modern lithography. A track here. This piece of equipment only handles the photoresist. It coats the wafer. You're talking, they measure these thicknesses in angstroms. An angstrom is a tenth of a nanometer. They develop it. They print it. They bake it so that we can replicate that pattern. The other piece is this here. It's called a stepper. It's called a scanner. That's the piece of equipment that actually manufactures, actually prints that pattern onto the surface of the wafer. This here, modern one, $35 million. That's not such a big deal as semiconductor factories. Eighteen month lead time. That's a big deal as semiconductor manufacturers. Especially because the lens sets on these, if you think about it, you're printing the same pattern hundreds if not thousands of times a day. Think about a camera lens. Can you wear out a camera lens? When we're talking about this level of precision, you can start to wear out the lens sets. You're shooting photons to the exact same spot on the lens over and over and over again. You'll wear the lenses out from photonic erosion. It's not that they don't work. It's that they aren't accurate enough anymore. It takes a couple of years. You're starting to see it though in people that use 8 inch still. Steppers are wearing out from lenses are wearing out. Modern technology uses 193 nanometer light. If you've been paying attention, you know we're not making transistors at 193 nanometers. We're making things smaller than the wavelength of light we're using to print the features. That makes life hard. That makes lithography weird. We get cool stuff. Lithography technique improvement one. Optical proximity correction. If I want to print this L shape on a wafer, you'd think I'd put that L shape on a mask. If I do that, I get that shape. That doesn't work. In some areas it's bigger. It doesn't like internal corners. It doesn't like external corners. This shape sucks. Let's try again. What if I printed that shape? That shape is numerically determined, basically calculated in a supercomputer. They do it on almost every single layer, every single mask, every single device. It prints a shape that looks like that. Overlay here the tan is the old shape. The gray is the new shape. That helps us immensely because still we're using light that's bigger than the devices. Next step, anti-reflective coatings. Look at the top. These are large features used to demonstrate this technique. On the left, this is without the coating. What you're seeing here, you see that repeating pattern on the wall? That's the photon oscillating. Without the coating, it bounces back. It might bounce back. It does its own thing. If we put a coating called anti-reflective, there's lots of different terms. This one's copyrighted. I'm using it anyways. If we put a coating on the bottom, we control the reflection, we play with constructive, destructive interference, we make that. That's an improvement. This is a big feature. The top one's a big feature. You can see the pattern. This I could still make a device out of. Let's go to the bottom. The bottom is when you make it to a normal device size. This is without. That looks like crap. This is with. That looks like railroad tracks. This is huge enabling technology. The next enabling technology, I'm going to talk about two here at the same time, is equipment advances. What you're seeing here is a couple of pictures about immersion lithography. Have you guys heard of immersion lithography? It's the big thing. Intel's doing this now. Wow. Basically, we're taking advantage of the effect you get when you try and throw a rock at something in a pond. It misses. You get refraction. Water has a very different index of refraction than air. This is our lens. You can follow the individual beams of light. With air, they're all spread out. With water, we can use water, a layer of water between the lens and the wafer, pinch them together, better quality control, and using that same 193 nanometer light, we can theoretically, physically make smaller features. Getting this to work took a decade. They've been working on this for years. There's two different theories on how to do it. One of them is dip the entire wafer in water. That's really problematic because you have to move the wafer around. It means you're getting a lot of ripples in the water. The water moves around. When the water's moving around, you can't print straight through it. Instead, the generally adopted solution is recovered water. It's in a lot of ways worse, but it works. They don't dip the whole wafer. What they do is they have a feed side, what they call liquid supply, and liquid recovery. They establish a bubble of water between the lens and the wafer on the stage, which moves it from chip to chip continuously. Part of the major delay was producing water clean enough to do this. They do it now. It's incredible. I'm blown away that they actually got this to work. The other one that you're going to start hearing about in a couple of years, there was a press release this week. Intel just invested a billion dollars in making this technology work. ASML is another company that makes these things. EUV. EUV means extreme UV. We're pushing the wavelength of light that we're using to print these down and down and down. The smaller the wavelength of light, the better we can make these features for all the other reasons we talked about. The problem with EUV is we're talking about extreme UV light that you can't do it in an air environment, which means you can't use immersion because all the water evaporates. EUV is so weak as a light source that you have to do it under vacuum or the wavelength, the wave won't propagate. This is up in Albany. They've been releasing some pictures of this. This is currently, as far as I know, the only EUV development tool. This is just the stepper. This is the part that does the printing, not the coding. That's a human being. This is the tool. This is one of these right now. This is what you're going to see in 10 or 15 or hopefully 5 years, because if not, we're in trouble. Ion implantation. I talked about gates and sources and drains. The sources and the drains are what we use to generate a transistor that behaves the way we want. To do that, we insert dopants, lots of different materials into the surface of the wafer. They used to do it with what they called spin on glass and the diffusion effect. You'd spin a contaminant on the top over a layer of lithography and then you'd bake the wafer and using the properties of diffusion, the wafer would suck it in. Nowadays, they use ion implantation. Ion implantation is the LHC size down. It is literally a particle accelerator. You take the gas that you want, you put it in here, you run it through a particle accelerator, and then you shoot it and embed it atom by atom in the surface of the wafer. Materials for this include gasified arsenic, xylene, which was initially, the story that was told to me was xylene was developed as a nerve gas. Now we use it in semiconductors. The wafer is about 400 degrees C and these things use permanent magnets that are very large and run at about 400 amps. The people who work on these are weird. The people in the fab who don't work on these stay far away. There's the constant historical rumor that is not supported by any statistical fact that the people who work on these only have girls. They've disproven that. Nobody believes them. Chemical vapor deposition. If I want to put a layer on the surface of a wafer that's very controlled, how do I do it? Chemical vapor deposition is one of the three ways to do it. Physical vapor deposition is another. That's starting to go away because it's imprecise. Imprecise is a relative term. Chemical vapor deposition, I have usually an argon curtain, an argon isolation gas, or something inert. You could theoretically use zeon, neon, it doesn't matter. Anything from the far right end of the periodic table. Then we start flowing other gases. We might flow, you know what, I'm not even going to say that. You flow two compounded gases that form a chemical reaction. Usually it's a surface limited reaction. We're doing a chemical reaction on the surface of the wafer that literally causes the layer of what you want to organically grow. Usually it's a temperature. You can control growth rate through temperature. You can control uniformity through temperature. Uniformity, I didn't mention uniformity. We talk about building a 300 millimeter wafer. We can control thickness better in a lot of ways than we need. But you have to control uniformity. If you talk about something that's, we'll say 5 nanometers thick. A layer that's 5 nanometers thick. If it's 5 nanometers thick everywhere on the wafer, you're a happy camper. The transistor will behave the same everywhere. If it's 5 at one point, 4 at another, 3 at another, 6 at another, you have an infinite number of varying different transistors. Uniformity is a big deal. Chemical vapor deposition is very good at uniformity. Something that's better at uniformity is called atomic layer deposition. This is what I think most companies are starting to use now for any thickness and uniformity critical layers. It's basically not dissimilar to the concept of epoxy. It's two parts. You flow one part, one pre-reactant over the surface of the wafer. Then you evacuate it using a vacuum pump. Then you flow the second. They react. You pump out the byproducts and you're left with one layer of atoms or molecules on the surface of the wafer. It's incredibly conformal. Conformal is huge because you start to get things that are very tall and very narrow. What you're looking at here is kind of a test structure. 200 nanometers right here. Let's think about that. We have the exact same thickness up until it pinches all the way around. Chemical vapor deposition really can't do that. Physical vapor deposition really struggles with it. When we zoom in here, you can see layer by layer by layer by layer. It's really neat. It was developed in the 1960s in Russia. In about 99 or so, they finally started to figure out how to use it. It started to really come into play, I'm going to say around 2005, 2008, somewhere in that range. The benefits are twofold, like I said. The first is conformality. It's the same thickness throughout the entire length of the layer. The other one is when we're doing it layer by layer, thickness control becomes really easy because we just add or subtract layers. We don't have to worry about timing nearly as much. You can do a lot of different materials with this. Unfortunately, you can't do... You kind of have to engineer the reactions from the precursors. It gets a little complicated. Part of the problem is you can't do things like silicon nitride. Silicon nitride is a very common material to use. It's what's called an etch stop in semiconductors. You use an etch stop to control the shape, the depth, the profile of things that you're removing from the wafer. They call it an etch stop. Silicon nitride you can't do. As far as I know, you can't deposit silicon dioxide either with ALD, atomic layer deposition, which up until very recently, silicon dioxide has been kind of the standard dielectric or insulative material for chips. I'm doing okay on time. Okay. Enough science and me talking. I mentioned foops. Let's watch a video and see how this works. Hold on. I kind of mentioned foops. This is a foop. 25 wafers. I'd say you're talking $60,000 in revenue from a bleeding edge wafer in terms of revenue and chips and memory. 25 wafers in a foop at $60,000 makes about $1.5 million. This is a bad day. Concept one. Don't do that. Concept two from anyone who's worked in the technical field. The radius of blame. If you notice the time clock. Can you guys see the time clock there? It's 5.30 in the morning. What happened here? An engineer's day just got very bad. If he's not up already, the engineer got woken up now. I'm not kidding. No cameras. At least one of the places I worked, we had phones. They want to be able to get in touch with you 24-7. When I got my phone, it was a Blackberry. It had a hole drilled in the back where there used to be a camera. You probably VoIP. They're trying to move away from using radios, which they used to use. Radios will screw up the tools. EM from a radio will shift all of your parametrics. It may even shut down the tool. What happened there? We mentioned foops and wafer handling and subclass one. The tool has a robot arm that does all the wafer movements. The robot missed. The reason there was a video camera there. Video cameras are not common in fabs. They just aren't. Most likely those weren't real wafers. Those were test wafers, what they call cycling wafers. They were trying to figure out what the handling problem with the tool was. They found it. The robot most likely had a misalignment. When it tried to put the wafer in, it holds the wafer using vacuum. It hit the foop rather than inserting it cleanly. Normally the foops are locked to the tool. If it had been locked to the tool, it would have been worse because the wafer would have broken inside the tool. Making it clean again may not ever happen. It's bad. What they did there was they unlocked the foop so that if that happened, they thought it would probably move or shift or catch the wafer. I doubt they planned that or they wouldn't have been running it. That's kind of fun. The steps. Here's what a modern transistor kind of looks like. First thing is we have our substrate. We have the substrate here in blue. First step that always happens nowadays is what's called shallow trench or silicon trench isolation. The devices are so small, so close together, so kind of not behaving like we want them to, we can just keep control over them, that they have started to do things where they basically insert an insulator between each device to isolate. It prevents crosstalk. It prevents leakage. It prevents one transistor from turning on another transistor. That's the first thing that happens. The second thing that happens is we put down our gate insulator. Here's a part that we know. We had six parts. We're going to turn it into a lot more parts. The gate insulator goes down and it does two things. One, it is our gate insulator. It isolates the gate of the transistor from the body of the transistor so we can make it work and not have a short. Two, when we open this up, it self-aligns for us all of the steps we're going to do afterwards. The gate insulator is highly critical and because of that they want everything to align with it so they do this step first. Then we deposit our gate. Gate material for years and years and years has been a thing called polysilicon. Hold the question until the end. Thanks. There's a lot in here I want to get through. It's been polysilicon which is a different crystalline version of the silicon we use as a substrate. It's more electrically conductive. It's tough so it can stand up to all of the future processing. That's what they've been using. They're going away from that now. We'll talk about that. We deposit our source in our drain. We dope our source in our drain. We begin to form with an ion implanter the regions that we want to connect the transistor to that we want to be a transistor. Then we form what's called a spacer. Spacer does a bunch of things. It's not electrically really part of the transistor but it's absolutely necessary in modern transistors because it contains the gate. It also narrows these openings which becomes really important when we do what's called our deep source and drain. The initial dopants here were very very light. Then we do a heavier doping. This allows us to begin to, rather than having a single region for the source and a single region for the drain, you're getting very much towards custom profiling. It's a curve rather than, analog versus digital sources and drains is a great way of looking at it. Then we form our SALISIDE. So at some point we have to connect these transistors to the outside world. If you think about a city, the transistor is your house. Everything that goes above it and allows the transistor to talk to the outside world is the streets, the highways, it gets progressively bigger. The SALISIDES, what they do is effectively, they're kind of a mix of usually a metal and silicon. They form a I guess a kind of a gap coverage so that we can actually get them to talk. We do it on top of each, the source and the drain, and then on top of the gate. Then we drive the dopants. So we talked about the two different, these are really like fourteen different implants to get this the way we want. Then we set them. We heat it up at a very high temperature over a thousand degrees C for less than a second and diffusion happens and everything moves around and we end up with very much a profile in here that can channel the locations and the densities of electrons and holes very much exactly where we want them so we can control things like the leakage, the threshold voltage, things like that. Then we deposit a dielectric. At this point, we're done making what we would call the device down here. Now we begin to connect it to the outside world. So the first thing we do is we seal the whole thing. That happens so that they can't leak. We don't want electricity getting from one to another and we want to be able to isolate them. Etch trenches and contacts. This is the first step in having something that it can talk to. We deposit a metal in there. We fill them, what we call fill contacts and trenches. We have a device. Then we do back end processing. So at this point, we have your house and we have your driveway. Then we start building what they call metal layers, which are the back end processing that I'm not going to get to really here, which is what interconnects individual transistors, individual devices into a logic circuit, into logic circuits, into memory, into cores, into everything you need to make a computer chip out of one of these. I talked about these as like, what, 10 or 11 steps here? These aren't steps. These are what we would call, in fab parlance, segments. Like this, 14, 15 steps, if not more. This whole set, by the time it goes to what you would call the back end, it's about three weeks later, if you're good, and somewhere in the range of, I'd say, 500 steps. I'm putting a range on it, but 500 steps. We've done 500 different things, 500 different tools to the wafer. I have in the backup slides, if you want to go through it, how you build those shallow trenches without any metrology, quality control, error checking, inspection, it's at least 13 different steps. Just the physical actions required to put those trenches, which are probably the simplest feature on here, in place. That's what it looked like when we talked about it as a theoretical device. This is what it looks like now. Here is what it looks like in a SEM picture. You can start to actually see the features. Here are those trenches. We talked about aspect ratio. Very, very tall, but very, very narrow. You can see these are the contacts that we talked about, the last step that connects to the outside world. Here, that little kind of white dot, that's our salicide. Here, sources and drains. Everything in here exists. You can probably see in here, this is like the transistor itself. This is the thing you're probably thinking of. If you look at it like this, let's zoom in a little more. This is a 2010 era 60 nanometer device. Right now, I think Toshiba has a 14 nanometer RAM or memory technology that they're starting to manufacture. That's a fifth or a fourth of this size. Here is the zoom in of our source, our drain, our gate, our salicide, and then our contact. 60 nanometers wide. This isn't a whole lot of fun. This doesn't tell us a whole lot. Let's zoom in more. Here's the gate. You see that? That's 1.2 nanometers. You've reached a point, at this point, this is using a traditional silicon dioxide insulator, gate insulator. They don't measure that in nanometers. They don't measure it in angstroms. When you're here, you talk about monolayers. Want to guess what a monolayer is? It's a layer of atoms. That's four. How do you put a tolerance on that? Three probably shorts out. Five probably won't connect. It takes me a minute to process this stuff, so you guys are fine. The length between the source and the drain, that channel that we talked about, on this device, it's 182 monolayers. 182 atoms between the source and the drain. This device, like I said, 2010. I'm not really sure where this came from. It was in a research paper. They quoted the clock speed of the chip that this came out of as 10 gigahertz. I don't know if that's right. I don't know if it's wrong. I don't care. They also gave a really interesting number, which is the transistor speed. Everybody thinks about clock speed. You think about how many gigahertz is my processor. This is a 10 gigahertz clock speed. It's a 200 gigahertz transistor speed. That's not uncommon. You're talking these things are switching on and off in the picosecond range. That's, to me, really cool. What does that look like? Here's Zoomed In. This is what it looks like in the context of your whole chip. That little chip you have inside your computer. If you cut it open with electron beam machining, this is what it looks like. Here, this is Intel 22 nanometer. They publicly released this. Don't worry. Here is Apple's 45 nanometer process for Samsung. That's in your iPad. At the top, you can see the very large metal layers. This is what the outside world connects to. This is what the packaging connects to. Metal layers get inherently smaller and smaller and smaller and smaller. This is all back end. All we've talked about is the green part here. You guys see that down there? Those are the devices. That's all in one package. This is, I estimate, 100 micron vertical thickness. Here's the same thing over here. You can see the contacts there. The tall, narrow things down there. Then you can start to see the individual devices and the parts down there. That's what we're making. That's what all those individual parts are in the front end. Modern improvements. That's fairly modern. Where are we going in the last four years? Where are we going in the future? The goals are threefold, really. Make off, offer. For a digital device, it's a little weird, but we're reducing leakage. We're making it so that when we tell it to be off, it's off. We want to make the difference between on and off sharper. We want to make our ability to turn things on and off faster. It means we can go faster and we can start changing other features of the transistor. The reality is, these aren't independent parts. Every single point on here is related to every single other point. If we can make this sharper, we can inherently retune our process to make off, offer. The other thing is, make on sooner. If we can make on and off sharper, if we can make off, offer, we can start making on sooner. We bring it down the voltage scale. It means we use less power. We have to ramp that voltage up. Even if it's a picosecond. Even if it's half a volt. We have to ramp that voltage up from zero. That takes time. It doesn't take long, but it takes time. If we can lower our threshold voltages a little bit, we're going to get a faster chip. We're going to use less energy, because energy is cumulative, in all that power we take, ramping up the voltage. Every change that we make is really to change one of these three things. First one, strained silicon. I forget the year people started doing this. It was like 2004. It's controlling in a way, the electrical properties of silicon. You deposit a layer on top. Here's our silicon atoms. They're this close together. We deposit something like silicon germanium on top of it. I guess this picture is kind of upside down. It stretches our silicon out. Depending on the device type, we might want to stretch it out. We might want to push it together. We can use that to control the electromobility of the silicon. We can make things faster. We can make things slower. We can do whatever we want. This is credited with a 35% improvement in transistor speed. One step. This is actually about 40 steps, but one design change. Let me say that. This is strained silicon in practice. Here's our transistor. Strained channel. We put it in there. We spread the silicon atoms out. We've created less traffic. The problem is we have to do other things, because less traffic means it'll leak more. The ability to have less traffic means we can start doing other things. We also start straining the source and the drain. It allows us to do even more detailed control than, and this is very high level, but very more detailed control than the dopants on how the transistors behave, how the source and the drain behave, what the electrical properties of them are. High K metal gate. Have you guys heard of this? Intel pimps this very hard. Other people are doing it as well. It's not just them. A couple slides ago I showed a 2010 era transistor with a normal gate. It was four atoms. You can't manufacture really thinner than that with any sort of quality control. The only way to do it is we need it to act electrically like it's thinner, so we make it thicker. We move from silicon dioxide to other materials with different coefficients that allow us to make it thicker. We'll make it electrically act thinner, because it's really just gotten too thin to be practical. The material changes. Here's what it looks like. Silicon substrate. Here's our gate. You can see metal gate, which is the second technology. We'll talk about that in a second. Here's the high K. We had four monolayers. You can't even see it. There's a lot of monolayers there. There's a lot more. That's good. It's one of the areas where making things bigger makes things better. It's rare in this world. The other one is metal gate. Really these are two technologies that got introduced at the same time because of some secondary manufacturing reasons. The metal gate is here's your high K dielectric, and you're starting to do different things in here besides polysilicon. The advantage is metal has far lower resistance than the polysilicon. It's more efficient. We can do things faster with lower leakage. The difference is it's very touchy. That deep drive step that I talked about where you're moving dopants around near the end of your manufacturing process will destroy your gate if you're not careful. You have to be very, very careful. It's very, very fragile. Metal was actually the original material they used back in the 70s and so forth for gates. They got away from it because it had manufacturing issues. They don't have a choice now. They have to go back to it to keep the improvements up of what they want. Here's how it looks. The gate gets taller and then this goes from being one step with something stacked with a salicide stacked on the top of it to I don't want to reveal anything, but a lot of different steps, a lot of different materials because what you're doing is you're engineering an electrical field here by how you stack metals here and how you flow electricity through it. We can control that field better. We can target that field. There's been some theoretical research done on basically using antenna theory where it's normally a field is fairly ubiquitous, fairly circular. FM antennas, they can do directional antennas, interference. They're starting to talk about using that here so that our field goes here and doesn't go here and here. That's hugely beneficial because we can put transistors closer together. Order of operations. Going back to when I kind of went through these are the steps. The gate insulator was the first thing. That doesn't work anymore with a lot of the new technology. The gates are fragile. The high K gate insulators are fragile. The metal gates are fragile. We build them last now, but we still need that gate there to define our transistor shape. We move from what they call gate first, which is where we do the gate first, to gate last. What gate last really is in most cases gate first and then do it again last. We build the gate. Then we remove the gate. This creates its own problems because those spacers are still there. This is an overdramatization of what's going on, but it works. The spacers are still there, but we have nothing here. We might have a little layer of silicon dioxide still in there, but we don't really care. Then we put our high K gate in. Then we put our hole gate in. Because we have those spacers there, we have to be very careful of how we fill this. This is where ALD comes in, because otherwise we end up with a big open what we call a void, a hole inside the gate. That's not good. It doesn't work the same. We build everything else normally. The nice thing is in some cases you can get rid of the salicide on top of the gate, which does remove steps. Because it's metal, it's easier to connect to. Depletion. Up until now we've talked about building things on our nice blue substrate. The problem is all of that energy, all those electrons can leak around in there because silicon is a semiconductor. It's not really electrically conductive, but it's not really insulative either. It's kind of in the middle. We take advantage of that. When we start to have problems with things leaking all over the place though, we want something to build on that is more electrically resistive. We want to totally customize everything about this transistor. Silicon wafer isn't a good starting point. First thing we do, we put a nice layer of dielectric down. We just say to heck with this wafer, or we might even change out the entire wafer. Say we're not going to use silicon anymore, we're going to use something else. Quartz is one of the ones that's been proposed. Then we put our own substrate. Then we put our own semiconducting material down. At this point we've just replicated the work of the wafer, but in a much, much more controlled fashion. This is the exact thickness that we want. It's the exact material that we want. We can dope it the way we want. We have exactly what we want for a starting point. Then we do our normal isolation trenches. At this point, I now have almost a Faraday cage, in effect. It's not a Faraday cage, but it kind of is, where I can build my transistor. It's isolated on all three sides. I don't just have the side isolation like I do now. I've isolated the bottom two. Electrons can't escape out the bottom. Then, everything else is the same. It's just compressed. It's a lot smaller area. We can control it a lot more. It ends up with the same transistor, sitting on top of a nice piece of insulative material. It helps everything. Here's the last one. Intel released these in 2011. The press release was like, there, you've been working on it since 2007 or before. FinFETs. Everything, as I said, is about turning things on and off faster, better, offer, honor. We have this here. This is our standard design. It's planar. The gate is on top. The gate is basically interrupting flow this way. Think about a lens on a camera. Everybody familiar with camera lenses? You have your aperture. If I had a gate aperture and I just closed it from the top, that'll take a certain amount of time for it to travel the distance. Instead, they do spiral apertures. If I have an aperture in a FinFET on all three sides, I have gate on all three sides, I can close that off much faster. I can generate the field much faster. I can improve everything about the transistor. This is what they look like. You're now growing silicon fins into space. What you're seeing here is they're actually starting to, rather than building one transistor, they're building one transistor that they can... They used to use different size transistors, different size planar transistors for different amounts of power, different voltages, things like that. In this, they've moved away from that model. You make one size fin. It's very hard to grow the fins. We don't want to try and grow two or five different sizes. They make one. Then they link them together like this. What you're looking at here is you see the ones that go in this direction. Those are the fins. Those are our source and our drain. They just stick up. You can see here, they stick up. Electricity still flows in the same direction. Then we have our gate. Our gate surrounds all three sides. You can see that here. Here's our fin. Now we have gate on all three sides. Everywhere you look, there's a lot more gate, a lot closer to the source and drain. What does that do in terms of performance? Power 50% lower while also, not or, also being 40% faster. The trade-off? It sucks to build these things. I don't know how Intel does it. I wish I did. I wish I could tell people and find out. I have my guesses. I don't know. It's incredible. Here is the black line's traditional transistor. The blue lines are choices of what we can start to do with the tri-gates. This is the first generation of tri-gates. It goes even further. You can theoretically do a gate all around, which means you have to build a gate on the bottom of the transistor too, which means you're doing gate first, gate in the middle, and gate last. I don't know of anyone who's gotten the manufacturing of that right yet. Where are we headed? May of this year, Paul Otellini, who is, I don't know what he is at Intel anymore, but he's at Intel, I think. He may have retired. Disclosed in a quarterly earnings call that they're doing 7 nanometer device R&D. In 2011, a number of different companies started selling FinFET 22 nanometer transistors. Remember that human hair? 40 nanometers? Yeah. 14 nanometer is on track, from what I've been told, for 2013. In two years, we can go from 22 nanometer to 14 nanometer. It's not really a structural change, because they don't have tri-gates right yet. Nobody does. Labs don't. It's really a refinement of everything. Some people are talking about transitioning to 450 millimeter wafers. That's those half meter diameter wafers. 2015, this is in development. This is not in research. This is in development. If you know Bell Labs, you know the difference. Lithography uses, they're talking about using something called quintuple patterning. We talked about lithography. If I shoot lithography once, I end up with something that looks a certain way, patterns a certain way. If I use a different photoresist that requires, rather than one photon, and I polymerize an individual strand, it requires two. That's double patterning. This is a horrible description of it. Go look it up on Wikipedia, because the people who write these things on Wikipedia work, I don't know who they work for, but they work for somebody who knows what they're talking about. Quintuple patterning is taking five shots of a lithography tool to generate one thing. There's some uses of averaging, of combination of different masks, different techniques, so that you can use all of those together to generate what you want. At this point, that's theorized. Semitext says high K, that thicker gate that we used, is now a monolayer. One. One atomic layer gate dielectric. We go back again. High K becomes ultra high K. We just find a different material, because if they can do that, I'm going to give somebody a high five. Lots of problems here. Intel and IBM have publicly discussed solving the problems of 11 nanometer by skipping it. At that point, we're no longer in microelectronics. We're in nanoelectronics. 2017, 2019, that's what they're talking about doing research on now. The device size, 7 nanometers. You can't get away from using EUV. The UV light they use now can't reach that at all. It just falls apart. EUV, like I said, doesn't work. Intel just invested a billion dollars in ASML, who's a major vendor, to try and make EUV work. It doesn't work. There's a lot of theoretical people in the field who say it will never work, because you're trying to use a photoreactive polymer in a vacuum chamber. Does anybody ever know anything about vacuum chambers? You're talking about something that's full of solvents. When you put it on the wafer, it will outgas. It's how do you prevent everything from outgassing? Because if you have outgassing, outgassing above the wafer is in between the wafer and the lens. You now have gas where you didn't want gas. Nothing works. That'll be interesting to solve. Then things get worse. Electrical interconnects start to have real problems just because of making things that are electrically conductive that small. They start talking about optical interconnects. They're talking about using, rather than really what I would call digital or quantum transistors, to more of what they're calling interference transistors, where the electrons interfere with one another and kind of quasi-turn it on and off. They don't really turn it on and off. The transistor thinks it's on or off. It's still flowing. They're controlling where electricity's coming from in constructive and destructive ways. I kind of ran off the bottom here. 2022, 4 nanometer. There's a lot of ideas here ranging from quantum to things that are more exotic than quantum. Right now, anything that's built at this size knows, wow, I'm actually right on time, is done using a scanning, tunneling microscope. What they're doing is they're not building things. They're manually stacking atoms to make a transistor. From what I've seen, the current winner is a group that built a 38-atom transistor. Why is this here? Well, here's my take. Every single computer chip, every single thing in your pocket uses this stuff. This is kind of how I got interested in it. I'm interested in coding. I'm a mechanical engineer. This was a good fit for me. Your car has these things in it. Everything has it in it. I want to know more about this. I thought you guys might want to know more about it, too. I talked to a couple people, and I just started talking about it because I really love this field. They just sat there like, oh, my God. I thought, well, yeah, I know, right? I thought, wow, you guys might think that, too. Here we are. Last slide. Let's do questions. I got nine minutes. I actually did this right on time, which is great. Questions? I have my Moore's Law t-shirt on. That's the wrong question to ask. I'm sorry. Moore's Law isn't just about size. What it is, it's about density. There's a lot of things that go into density beyond just how small we can manufacture something. But it's not just about density, either. It's about price. As these things mature, they do get cheaper. Moore's Law has got, I'd say, a decade left in it before it becomes a problem. That's more going to be cost-driven than anything else. Other questions? You can ask anything. I have a bunch of backup slides. Yes? Neutrinos are a problem. One of the standard research and development quality control tools is you set two chips running on the same test routine, take one down in a mine, and take one up in an airplane. That used to be a problem. Everybody has taken the approach of, it's a problem, we'll deal with it with software. We'll deal with it with error checking and circuit design. Because if you look at the statistics of those neutrino collisions, it happens. It does happen. But the odds of it happening in the same place in two different parts of the chip at the same time are highly unlikely. There was another thing I wanted to say, and I don't remember, so I'm sorry. Others? Yes? He asked about dopant migration. If I'm going to go backwards here, we'll do it from depletion. When he says dopant migration, we have those, I should use the laser pointer rather than pointing, these suckers, the sources and drains. When we put impurities in there, they do have a tendency to, over time, move around. It's the law of diffusion. It's a physics problem. The hotter the chip gets, the more likely it is, higher usage cycles. I would respond to that by saying the fully depleted will help, because there's less electromobility in these areas. It means they're less likely to move around. The other thing is... It depends on which way you're straining. It's physics. I don't think people keep these chips long enough for it to be a problem. If you look at the refresh cycles, if you're talking a bank, somebody that's high frequency trading, the NSA, they save money. The chips are getting so much better, so much faster, from a power alone standpoint. From a power and computational density, instructions per watt, computations per watt standpoint, that they can replace them every 18 months and make money. It saves them money to replace them every 18 months. In the back. The question was, R&D costs are spiraling ridiculously out of control. What's gonna happen to competition in the industry? Currently, to answer your question, there is more than one lithography company. I know you... I consider it a problem as a hacker, as a person who wants to buy these things for the least amount of money possible. It's not so much the cost as the difficulty. I mean, you're going to see contraction, but there's I think an inherent natural trade off in these things of the companies that do them, the companies that do the manufacturing and do the tool development, are very, very closely interrelated. Because of that, they have a very clear path in their mind. They don't always tend to think creatively like hackers, like academics do. You're seeing with atomic layer deposition is a great example. All of the major tool vendors, and there's I'd say five major tool vendors, have ALD systems. There's also been sprung up a lot of smaller companies that have incredible ALD tools because that's all they do. Because they have people who did research on this and they weren't tool developers, they were scientists. And they've hooked up with engineers and they're doing really neat things. From a standpoint of the Intel's, the Global Foundry's, the IBM's, the TSMC's, you're going to see narrowing. The industry itself though, at least outside of, I'm going to say outside of logic, is fairly competitive. And that will, I think, keep prices down. But I'm not a business guy. I'm not an economicist. There are definitely some structural problems like 450 is going to cost anybody who wants to A lot of money. And so you will see some contraction. All I can say is wait and see because I don't know. Anybody else? In the way, way back, who I can just barely see. I can't hear you. I can't hear you. So he asked if we'll see fib, which is focused ion beam. Huh. The physics right now, the theory right now says we almost have to. Whether it's I don't know how they make it realistic for a manufacturable technology. So you guys should go look up focused ion beam. It's cool. It's how you can basically atom by atom manufacture things. I don't know how they can make it work. So it's 12.57. I got if there's one more question and then I want to. Oh, I'm sorry. Can I do one more? Right there. I don't know. It scares me. That's the simple answer. Alright, thanks guys. I don't want to run over.